Referring now to FIG. 1, a computer system 10 is shown. A plurality of computing devices 12-1, 12-2, . . . 12-M, collectively referred to as computing devices 12, are connected by a communication cable 14. The communication cable 14 connects to differential signal bus interfaces 16-1, 16-2, . . . , 16-M, such as small computer system interfaces (SCSI interfaces), associated with respective computing devices 12. The interfaces 16-1, 16-2, . . . , 16-M are collectively referred to as the interfaces 16. The computing devices 12 may include a host controller, disk drive and/or any other device having a compatible SCSI interface. Terminators T-1 and T-2 include terminating bias resistors 18-1 and 18-2, referred to collectively as bias resistors 18, which are connected across conductors at opposite ends of the communication cable 14. In some applications, a single terminator T is used at one end of the communication cable 14. In practice, a plurality of cables 14 and terminating bias resistors 18 would connect the interfaces 16 to form a parallel data bus 20. The data bus 20 may have several channels that each carry a bit of data per cycle. The data bus 20 may include additional channels for control signals. For purposes of clarity, only one channel of the parallel data bus 20 is described herein.
Turning now to FIG. 2, an output driver 22 of the prior art is shown. The output driver 22 provides an output port 24 that connects to the communication cable 14 and the bias resistor 18. A p-channel field effect transistor (PFET) Q1 has a gate connected to a PFET predriver 26. A drain of the PFET Q1 is connected to a voltage source VDD. A source of the PFET Q1 is connected to a drain of an n-channel field effect transistor (NFET) Q2. A gate of the NFET Q2 is connected to an NFET predriver 28. A source of the NFET Q2 is connected to a reference voltage VSS. The connection between the source of the PFET Q1 and the drain of the NFET Q2 provides one node of the output port 24. A PFET Q3 has a gate connected to a PFET predriver 30. A drain of the PFET Q3 is connected to the voltage source VDD. A source of the PFET Q3 is connected to a drain of an NFET Q4. A gate of the NFET Q4 is connected to an NFET predriver 32. A source of the NFET Q4 is connected to the reference voltage VSS. The connection between the source of the PFET Q3 and the drain of the NFET Q4 provides the second node of the output port 24. Such an arrangement of the PFETs and NFETs Q1-Q4 may be referred to as an “H-bridge.”
When the PFET Q1 and the NFET Q4 are turned on, and the PFET Q3 and the NFET Q2 are turned off, then current flows in a first direction through the output port 24. When the PFET Q1 and the NFET Q4 are turned off, and the PFET Q3 and the NFET Q2 are turned on, then current flows in a second direction through the output port 24. As the current flows through the output port 24 in the first and second directions, high and low voltages are developed across the bias resistor 18. The high and low voltages typically range from +0.5V to −0.5V, and provide a data signal representing digital ones and zeros on the communication cable 14. Drive voltages applied to the gates of the PFETS and NFETS Q1-Q4 by the PFET and NFET predrivers 26, 28, 30, and 32, may be adjusted. The drive voltages determine a slew rate during transitions between the high and low voltages across the bias resistor 18. Such a configuration is described in U.S. Pat. No. 6,597,233, the specification of which is incorporated herein by reference. While the output port 24 of the prior art provides an adjustable slew rate, the actual slew rate obtained may vary undesirably depending on variables such as a length of the communication cable 14 and manufacturing variables of the PFETs and NFETs Q1-Q4.